| Advanced Logic - 40nm, 65/55nm |
40nm
SMIC is the first foundry in mainland China to offer 40nm technology. SMIC offers its 40nm Low Leakage (LL) process with three threshold voltage core devices and 1.8V, 2.5V I/O options to meet various design application requirements. The 40nm logic process combines the most advanced immersion lithography, strain engineering technique, ultra shallow junction and ultra low-k dielectric for maximum power and performance optimization.
Features:
- Core device options: 1.1V (LL)
- Three different Vt level core devices for flexible design optimization
- I/O device options: 1.8V, 2.5V (pure) with over drive and under drive capability
- Single-port and dual-port SRAM bit cells associated with memory compilers
- 193nm immersion lithography for critical layers
- Strain technique to enhance mobility
- Millisecond anneal for ultra shallow junction
- Up to 10M Cu/Low-k (k = 2.7)
- Wire bond and flip chip options
40nm Logic Standard Offerings |
| Standard Offering |
40LL (1.1V) |
| Core Device |
HVt |
√ |
| SVt |
√ |
| LVt |
√ |
| I/O Device |
1.8V |
√ |
| 2.5V |
√ |
| 2.5V OD 3.3V |
√ |
| 2.5V UD 1.8V |
√ |
| Memory |
SP HD SRAM (0.242μm2) |
√ |
| SP HP SRAM (0.303μm2) |
√ |
| DP HD SRAM (0.477μm2) |
√ |
| DP HP SRAM (0.600μm2) |
√ |
|
| |
65nm/55nm The 65nm/55nm logic technology combines improved performance and reduced power consumption with increased design possibilities and cost efficiencies. The 65nm/55nm logic process standard offerings include both Low Leakage (LL) and Generic Purpose (G) platforms. Both LL and G processes offer three threshold voltage core devices and 1.8V, 2.5V I/O options to provide a flexible design platform. Design rules, specifications, and a SPICE model are available for 65nm/55nm. Critical IP is ready for 65nm LL and is currently under development for 55nm.
Features:
- Core device voltage from 1.0V to 1.2V
- I/O device options: 1.8V, 2.5V or 3.3V
- Dual damascene Cu + low-k (3.0) as BEOL interconnect
- NiSi Process
65nm Logic Standard Offerings |
| Standard Offering |
65LL (1.2V) |
65G (1.0V) |
| Core Device |
HVt |
√ |
√ |
| SVt |
√ |
√ |
| LVt |
√ |
√ |
| I/O Device |
1.8V |
√ |
√ |
| 2.5V |
√ |
√ |
| 2.5V OD 3.3V |
√ |
√ |
| 2.5V UD 1.8V |
√ |
√ |
| 3.3V |
√ |
√ |
| Memory |
SP HD SRAM (0.525μm2) |
√ |
√ |
| SP HP SRAM (0.620μm2) |
√ |
√ |
| DP HD SRAM (0.974μm2) |
√ |
√ |
| DP HP SRAM (1.158μm2) |
√ |
√ |
|
| |
| 55nm Logic Standard Offerings |
| Standard Offering |
55LL (1.2V) |
55G (1.0V) |
| Core Device |
HVt |
√ |
√ |
| SVt |
√ |
√ |
| LVt |
√ |
√ |
| I/O Device |
1.8V |
√ |
√ |
| 2.5V |
√ |
√ |
| 2.5V OD 3.3V |
√ |
√ |
| 2.5V UD 1.8V |
√ |
√ |
| 3.3V |
√ |
√ |
| Memory |
SP HD SRAM (0.425µm^2) |
√ |
√ |
| SP HP SRAM (0.502µm^2) |
√ |
√ |
| DP HD SRAM (0.789µm^2) |
√ |
√ |
| DP HP SRAM (0.938µm^2) |
√ |
√ |
|
