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• Technology Platform
• Process/PDK
• IP Design/Service/Maturity
• Application Platform
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• AE Support for Customer
• Reference Flow
• Tape Out/Assembly/Testing
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• IP Alliance
• EDA Alliance
• Design Service Alliance
• Chip Assembly/Testing
Technical Event
Reference Flows

SMIC-Synopsys Reference Flow 4.0

SMIC-Synopsys Reference Flow 4.0, a chip-level flat design flow from RTL to verified GDSII, once again delivers a low power design. This time, Reference Flow 4.0 uses SMIC’s advanced 65-nanometer (nm) low leakage process with Synopsys Galaxy implementation platform and Discovery? verification platform.

This proven flow was validated using SMIC in-house-developed CCS (Composite Current Source) standard cell library, low power cell library, memory compiler, PLL and IO to illustrate a power-gating design. In addition, flow leverages Unified Power Format (UPF), an IEEE standard 1801 for defining low power design intent to improve the way complex SoC (System-On-Chip) designs can be implemented and verified.

SMIC and Synopsys collaboration has enabled IC designers to accelerate their designs into manufacturing, with flexible, lower-risk environment, faster time-to-market, targeting at SMIC 65nm process technology.

SMIC-Synopsys Reference Flow 4.0 highlights:

Simulation of power shutdown, signal isolation, data retention using Synopsys VCS + MVSIM + UPF at both RTL and gate-level.
Unified Power Format (UPF) flow.
Array-based power gating (MTCMOS) methodology.
Multiple-VDD, multiple-supply blocks.
Multi-Corner, Multi-Mode (MCMM) optimization.
On-chip clocking control (OCC) with at-speed test pattern generation (ATPG).
Multi-voltage, multi-supply Hercules verification.
Seamless integration, performance and capacity with the libraries and design rules required by SMIC's advanced silicon processes.

SMIC Reference Flow package includes:

Flow setup/execution manual and sample test case (a 128-bit AES encryption/decryption chip) to give customers step-by-step explanation on how this design flow works.

Reusable scripts and utilities that help customers implement their design with ease.

Most importantly, we have trained experts ready to support and offer you professional advice to bring your design to high-quality sign-off gds.

Anchored by Synopsys' Design Compiler, Formality, VCS, JupiterXT, Physical Compiler, DFT Compiler MAX, TetraMax, Power Compiler, Astro, PrimeTime PX, StarRCXT, Hercules, PrimeRail, and IC Compiler, the Galaxy Design Platform reduces design times, decreases integration costs and helps minimize risks inherent in advanced, complex IC design.

If you would like to know more about the SMIC-Synopsys Reference Flow 4.0, please contact your SMIC account manager, login to SMIC Now or send us a message.

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